Researchers, led by Xiaohang Li from KAUST, have developed a groundbreaking chip featuring 41 vertical layers of semiconductors, a significant advancement beyond the traditional trend of miniaturization in electronics. This innovation, detailed in Nature Electronics, allows for increased circuit density and enhanced performance, achieving 600% more logic functions in the same area compared to single-layer designs. As the industry approaches the limits of Moore’s Law, this approach offers a sustainable path forward for electronic devices. The stacked architecture promises flexible and energy-efficient solutions for future technology.
